The present invention relates to a power voltage regulating circuit applied to a semiconductor integrated circuit, and more specifically, to a power voltage regulating circuit applied to a large-scale integrated circuit which employs a transistor having a channel length of about 0.2 micron or less, from the 256 M bit dynamic RAM (DRAM)-generation onwards.
Since the 16 M generation, the DRAM has been employing a technique in which an external power voltage Vcc is regulated within it's chip, to an internal power voltage Vint which is lower than Vcc, and thus regulated voltage is supplied to each circuit. The reason for the DRAM employing such a technique is as follows. That is, the effective channel length Leff of the transistor has been shortened these days. If an external power Vcc is applied directly to such a transistor, the characteristics of the element are deteriorated, and more specifically, for example, the threshold voltage Vth is varied and the transconductance Gm is lowered. As a result, there is a great possibility that the DRAM would become defective within 10 years.
Conventionally, as a power voltage regulating circuit of a DRAM, a circuit shown in FIG. 18 or 19 is shown. The circuit shown in FIG. 18 is a type which generates an internal power voltage Vint from an external power Vcc with use of a p-channel MOS transistor serving as voltage regulating transistor, and in this circuit, the gate of the p-channel MOS transistor 180 is controlled with a comparison output from a comparator 183. The comparator 183 compares a reference potential VREF and a potential obtained by dividing an internal power voltage Vint by resistances 181 and 182, with each other. The reference potential VREF is a constant voltage which is not dependent on temperature or an external power voltage, and VREF is generated by using, for example, a band-gap reference circuit in the chip. The comparator 183 is designed to pull the internal power voltage Vint back to the set value by turning on the p-channel MOS transistor 180, in the case where the internal power voltage Vint becomes lower than the preset value.
FIG. 19 shows a circuit designed to generate an internal power voltage Vint from an external power voltage Vcc with use of a threshold voltage Vth of an n-channel MOS transistor 191 serving as a voltage regulating transistor. The gate electrode of the n-channel MOS transistor 191 is set to Vint+Vth. With regard to the operation bias for the n-channel MOS transistor, the source voltage is as high as the internal power voltage Vint. Therefore, due to the substrate bias effect, the threshold voltage Vth becomes as high as about 1.5V, and therefore the gate potential of the n-channel transistor 191 must be set to Vint+about 1.5V, for example, when Vint=2.5V, the gate potential must be set to about 4V. In the case where the power voltage Vcc is 3.3V, this 4V voltage must be increased within the chip, which require a pump circuit 192 including an oscillator which is not shown. In addition, even if the threshold voltage Vth varies, the internal power voltage Vint must be maintained at the preset value. Therefore, the gate voltage must be a potential obtained by compensating the threshold voltage Vth. In order to achieve this, a potential which is lower than the gate potential by the threshold voltage Vth, is generated by the n-channel MOS transistor 193, and another potential is obtained by dividing thus generated potential with resistances 194 and 195, to be compared with the reference potential VREF by a comparator 196. Then, the gate potential is varied to Vth by driving the pump circuit 192. In this manner, it is designed such that the internal voltage Vint is not influenced by the variance of the threshold voltage Vth.
Any of the above-described voltage regulating circuits are already used in practice for those up to 64 M bit DRAM, and therefore they are practically proved to be fully applicable. However, in the case of the circuit shown in FIG. 18, when the gate potential of the p-channel MOS transistor 180 used for reducing the voltage, drops to zero, in other words, when the potential of Vint is decreased lower than the preset value as a load current flow to the internal circuit, the power voltage Vcc is applied between the gate and source electrodes of the transistor 180. In the case of the circuit shown in FIG. 19, the gate of the p-channel MOS transistor used for reducing the voltage, will have a voltage no less than the power voltage Vcc, and therefore a high voltage is applied to the pump circuit 192 for generating the high voltage not less than the power voltage, or to the gate of the n-channel MOS transistor which constitutes a capacitor 197 shown in the figure. However, as will be explained later, there is a sufficient allowance with regard to the withstand voltage of the insulating film, and when the effective channel length Leff of each of these elements is set longer than those of Leff of the other circuits, a hot carrier resistance for the voltage regulating circuit itself can be made assured, making it possible to maintain the reliability of the entire DRAM.
In the case of DRAMs from the 256 M bit generation onwards, it is considered that a sufficient reliability of the device cannot be assured with the power voltage regulating circuit in some cases. This is because, as the size of the element becomes finer, the factors for the reliability of the device, change. More specifically, up to the generation of the 64 M bit DRAM, the withstand voltage by the hot carrier determines the reliability of the device, whereas from the generation of the 256 M bit DRAM onwards, the reliability of the DRAM is determined by the withstand voltage error of the insulating film of the transistor, rather than the above factor.
FIG. 20 illustrates how the power voltage Vcc and the internal power voltage Vint change as the size of the DRAM becomes fine, along with the hot carrier voltage VB.sub.HC and the insulating film withstand voltage V.sub.TDDB. As is clear from this figure, from the 1 M bit DRAM to 4 M bit DRAM, both the hot carrier withstand voltage and insulating film withstand voltage are higher than the external power voltage Vcc, and therefore the decrease in voltage is not required. By contrast, in the case of the 16 M bit DRAM, for an external power voltage Vcc=5V, the hot carrier withstand voltage VB.sub.HC becomes lower than Vcc, and therefore if Vcc is used as the power for the circuit, the hot carrier is generated, thus causing the variation of Vth or Gm (=Ids/Vgs). As a result, the life of the DRAM, which is set to 10 years or longer as its specification, cannot be satisfied. In order to avoid this, the voltage regulating circuit is provided within the DRAM, and the method in which the external power voltage Vcc is lowered to the level of the internal power voltage Vin by the voltage regulating circuit and then supplied to a desired circuit, is employed. Naturally, since Vcc is applied to the voltage regulating circuit itself, the transistor which constitutes this circuit is formed to have a large effective channel length Leff, so as to improve the hot carrier withstand voltage. This is also the case for the 64 M bit DRAM.
However, for the generation of the 256 M bit DRAM, that the withstanding voltage of the insulating film of the transistor becomes insufficient with regard to the power voltage Vcc, in addition to the aspect of the hot carrier withstand voltage. Therefore, it becomes no longer possible to apply the conventional technique, in which an internal power voltage Vint is generated with use of a voltage regulating circuit shown in FIGS. 18 to 19, and only the effective channel length of the device is elongated, so as to assure a sufficient hot carrier withstand voltage. More specifically, in the case where a circuit is formed of a transistor having a gate oxide film thickness (tox) of 60 angstroms, for a withstand voltage of the insulating film of 4.5 MV/cm (if an electrical field stronger than this is applied to the insulating film, the insulating film becomes defective within 10 years of use of this device), a voltage of 2.7 or higher cannot be applied between the gate and channel of the transistor. In order to avoid this, the voltage supplied to the circuit should be lowered from an external voltage of 3.3V to 2.7V; however in the voltage regulating circuit shown in FIGS. 18 or 19, the transistor itself, which is a part of the device, receives that 3.3V, and the withstand voltage error may be easily created at this part.
Conventionally, it suffices only if the hot carrier withstand voltage is considered, and the problem of which can be solved by increasing the effective channel length for the transistor. However, in order to lower the voltage for maintaining the withstand voltage of the insulating film, the thickness of the gate oxide film of the transistor of the voltage regulating circuit must be increased. In this case, not the approach in terms of design, that is, increasing the effective channel length, but the approach in terms of processing, that is, forming two types of transistors having different insulating films, is required. Such an approach for the process entails an increase in the number of processing steps, or an increase in the yield of the product due to the deterioration of the controllability of the process, which causes a great increase in the production cost.
The basic solution to the above problem is naturally to lower the external power voltage itself; however in practice, the power voltage cannot be so easily decreased due to a great number of limitations as the system.